Embedded memories occupy an increasingly large fraction of chip area with each progressing technology node. In fact, memories are one of the densest packed structures on the chip. However, densely packed memories are also more prone to structural issues. To increase the yield of the chip, embedded memories have redundant elements (redundant row, redundant column) which can be replaced with the faulty cell present in the normal address space. The numbers of redundancies provided to each and every memory are limited in number.
Validating that the chip was manufactured without any faults becomes an important task since the numbers of faults are increasing due to shrinking process nodes. Also, testing the embedded chip memories becomes challenging since the memory cells are packed closely together. Hence, built-in self-test (BIST) modules are permanently embedded in the design to test the memories when they are not in functional mode. Moreover, BIST becomes an essential part of the chip design in testing of these embedded memories, with each of the pre-defined patterns which are part of BIST finite state machine (FSM) detecting different kinds of faults present on the memory depending on the kind of memory that is being tested.
Memories can be repaired in couple of ways, e.g.:
Off chip repair: Most of the older technologies have an off-chip repair mechanism. In this method, a tester collects the failing information from the chip and a software algorithm analyzes the fails and gives out an optimal repair solution. Loading the repair data back into the repair registers can happen by blowing on-chip fuses with the repair data or by loading the repair information stored in flash memory by the processor into the corresponding repair register.
On-chip Repair: In these technologies, on-chip repair is provided as more faults are seen. Because of the many challenges, the on-chip solution seems to a better option as there is no need to off load the fail diagnostic information into the tester and load back the repair data back into the chip. According, this method reduces test-time, which is more valuable. Also, on-chip repair offers parallel testing of memories which will further help to reduce the Memory BIST test time. Another advantage of on-chip repair is the flexibility it provides for soft repairs of some of the faults present in the memories.